1. Field of the Invention
This invention relates to a semiconductor memory device, and specifically to a layout suitable for a synchronous DRAM (Dynamic Random Access Memory).
2. Description of the Related Art
A great feature of a synchronous DRAM is that it follows the architecture of other general-purpose DRAM and is activated at a high frequency of 100 MHz or above using a low-voltage TTL interface. Further, the synchronous DRAM is of a clock synchronous type and allows a pipeline operation by which burst data can be transferred even during a cycle in which an address is inputted and decoded. In order to perform these advantageous functions, one obtained by frequency-dividing a clock into 1/2, for example, is used inside the synchronous DRAM. Thus, the internal operation of the synchronous DRAM is synchronized with 1/2 of the frequency of an external clock, regardless of external-clock input conditions. Therefore, the synchronous DRAM is excellent in operating margin.
The synchronous DRAM alternately reads information from and writes it into adjacent data line pairs in synchronism with a clock signal. The data line pair at the time of its read operation has been precharged to VCC-VT (where VCC is the power source potential, and Vt is the threshold voltage of a transistor connected between each data line and a power source potential supply source) in advance. A small potential difference .DELTA.V appears between the adjacent data line pairs from the subsequent reading of data. In the write operation, one of the data line pair is supplied with VCC, whereas the other is supplied with VSS.
When the write operation is performed prior to the read operation in the synchronous DRAM, one of the data line pair is precharged from VSS to VCC-Vt, whereas the other is precharged from VCC to VCC-Vt. Since a parasitic capacitance exists at this time between one of the precharged data line pair and one of the data line pair adjacent thereto, the initial potential of the corresponding data line is increased to VCC-Vt+.alpha.. The term .alpha. reflects the degree of coupling that results from the parasitic capacitance. With such a device, there has been the possibility that even if information is thereafter read from a sense amplifier, the difference in potential .DELTA.V between the adjacent data line pairs has not become wide, so that data would be outputted erroneously.